74HC175 is a quad positive-edge triggered D-type flip-flop with individual datainputs (Dn) and complementary outputs (Qn and Qn).
The common clock (CP) and master reset(MR) inputs load and reset all flip-flops simultaneously.
The D-input that meets the set-up and holdtime requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appearat the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs includeclamp diodes.
This enables the use of current limiting resistors to interface inputs to voltages inexcess of VCC.
- Logic Type: D type Flip-Flop.
- Supply Voltage: 2V - 6V.
- Buffered-Positive Edge-Triggered Clock.
- Clock Frequency (Max): 35MHz.
- Logic Case Style: DIP.
- No. of Pins: 16.