74HC192 ( Presettable Synchronous Counter)

Introduction :

74HC193 is a 4-bit synchronous binary up/down counter. Separate up/downclocks, CPU and CPD respectively, simplify operation.

The outputs change state synchronouslywith the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is heldHIGH, the device will count up.

If the CPD clock is pulsed while CPU is held HIGH, the device willcount down. Only one clock input can be held HIGH at any time to guarantee predictable behavior.

The device can be cleared at any time by the asynchronous master reset input (MR); it may alsobe loaded in parallel by activating the asynchronous parallel load input (PL). The terminal count up(TCU) and terminal count down (TCD) outputs are normally HIGH.

When the circuit has reachedthe maximum count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to goLOW. TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise,the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW.

Theterminal count outputs can be used as the clock input signals to the next higher order circuit ina multistage counter, since they duplicate the clock waveforms. Multistage counters will not befully synchronous, since there is a slight delay time difference added for each stage that is added.

The counter may be preset by the asynchronous parallel load capability of the circuit. Informationpresent on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs(Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW.

A HIGH level on the master reset (MR) input will disable the parallel load gates, override bothclock inputs and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and aftera reset or load operation,

the next LOW-to-HIGH transition of that clock will be interpreted as alegitimate signal and will be counted. Inputs include clamp diodes.

This enables the use of currentlimiting resistors to interface inputs to voltages in excess of VCC.

Features :

• Logic type :  Counter.
• Supply Voltage : 2 -6V.
  
• Synchronous Counting and Asynchronous Loading.
• Two Outputs for N-Bit Cascading.
• Operating Temperature Range –55°C to 125°C.
• High Noise Immunity.
• Package type : DIP 16.